Cypress Semiconductor /psoc63 /USBFS0 /USBDEV /EP0_CR

The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.

0 (DISABLE): Ignore all USB traffic to this endpoint

1 (NAK_INOUT): SETUP: Accept IN: NAK OUT: NAK

2 (STATUS_OUT_ONLY): SETUP: Accept IN: STALL OUT: ACK 0B tokens, NAK others

3 (STALL_INOUT): SETUP: Accept IN: STALL OUT: STALL

5 (ISO_OUT): SETUP: Ignore IN: Ignore OUT: Accept Isochronous OUT token

6 (STATUS_IN_ONLY): SETUP: Accept IN: Respond with 0B data OUT: Stall

7 (ISO_IN): SETUP: Ignore IN: Accept Isochronous IN token OUT: Ignore

8 (NAK_OUT): SETUP: Ignore IN: Ignore OUT: NAK

9 (ACK_OUT): SETUP: Ignore IN: Ignore OUT: Accept data and ACK if STALL=0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.

11 (ACK_OUT_STATUS_IN): SETUP: Accept IN: Respond with 0B data OUT: Accept data

12 (NAK_IN): SETUP: Ignore IN: NAK OUT: Ignore

13 (ACK_IN): SETUP: Ignore IN: Respond to IN with data if STALL=0, STALL otherwise OUT: Ignore

15 (ACK_IN_STATUS_OUT): SETUP: Accept IN: Respond to IN with data OUT: ACK 0B tokens, NAK others

The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.

0 (ACKED_NO): No ACK’d transactions since bit was last cleared.

1 (ACKED_YES): Indicates a transaction ended with an ACK.

When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to ‘1’ after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register.

When set this bit indicates a valid IN packet has been received. This bit is updated to ‘1’ after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register.

When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to ‘1’ the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register.